1. Field of the Invention
The present invention relates to an electronic circuit, and more particularly, to an electronic circuit for suppressing a jitter noise in voltage Vdd in an integrated circuit (IC).
2. Description of the Prior Art
Integrated circuit (IC) designers nowadays pay much more attention to high speed and low voltage design issues. The parasitic inductance generated due to the packaging of an IC such as wire bonding has a significant influence on the internal circuitry of the IC. For example, a voltage jitter phenomenon is generated by the power. The voltage jitter phenomenon will reduce the circuit performance significantly, especially in IC designs related to high frequency and low voltage.
The conventional methods for suppressing the voltage jitter phenomenon include utilizing a better packaging scheme and utilizing a multiple bonding wire scheme (such as three-fold, four-fold, or five-fold bonding wire schemes). FIG. 1 shows a simplified block diagram 100 of the five-fold bonding wire scheme according to conventional art. In this conventional art, a chip 102 includes a pin 104, a plurality of power bonding pads 105-109, a plurality of bonding wires 110-114, and an equivalent capacitor 120, wherein the plurality of bonding wires 110-114 have an inductance value, and the plurality of bonding wires 110-114 are coupled to the pin 104 and the power bonding pad 105-109 respectively. The power bonding pads 105-109 are coupled to a power terminal inside the chip 102. Theoretically, the greater the number of bonding wires, the better the suppressing effects. The conventional methods apply the theory of more inductances connected in parallel generating a smaller equivalent inductance value, so as to reduce the effective parasitic inductance value. The purposes of these two conventional arts are both to reduce the parasitic inductance value and to suppress negative performance impacts resulting from voltage jitter.
Conventional methods utilizing a better packaging scheme or more bonding wires require more bonding pads, and thus a larger chip area to accommodate the increased number of bonding pads. Thus, conventional methods suffer from higher packaging and wire bonding costs. The competitiveness of the IC is based on the circuit performance and its manufacturing cost. Thus, improving IC performance while lowering cost is a perpetually important issue for IC design researchers.